The present invention generally relates to a ferroelectric memory, and more particularly relates to a ferroelectric memory including field effect transistors (FETs). In each of the FETs, source/drain regions are defined and spaced apart from each other on the surface of a well region within a semiconductor substrate. And a gate electrode is also formed over a channel between the source/drain regions in the well with a ferroelectric gate insulating film interposed therebetween.
Hereinafter, a known ferroelectric memory of the type disclosed in Japanese Laid-Open Publication No. 8-3166440, for example, will be described with reference to FIGS. 21, 22, 23, 24 and 25. FIG. 21 illustrates an overall arrangement for a memory array in the known ferroelectric memory. FIG. 22 illustrates a planar layout for part of the memory array shown in FIG. 21, e.g., well contact region (1) and array block (1xe2x80x941). FIG. 23 illustrates a planar layout obtained by removing the bit and source lines from the layout shown in FIG. 22. FIG. 24 illustrates a planar layout obtained by removing the word lines from the layout shown in FIG. 23. And FIG. 25 illustrates an equivalent circuit of the known ferroelectric memory.
As shown in FIG. 21, multiple array blocks are arranged to form a matrix, i.e., in a number m of rows and a number n of columns. The number m of array blocks, belonging to the same column, shares a single well region.
As shown in FIGS. 22, 23 and 24, multiple well regions 1, extending in one direction and in parallel to each other, are defined in a semiconductor substrate. In addition, multiple well isolating regions 2 are also defined to extend in the same direction and in parallel to each other. In this manner, each of the well regions 1 is electrically isolated from horizontally adjacent ones by the associated pair of well isolating regions 2. Also, on the surface of each well region 1, multiple element isolating regions (e.g., field oxide regions) 9 are defined at regular intervals.
As shown in FIG. 24, first and second active regions 7S and 7D (to be source/drain regions, respectively) are defined between adjacent ones of the element isolating regions 9 on the surface of each well region 1 with a channel region 8 interposed between these regions 7S and 7D. As shown in FIG. 22, the first active regions 7S, belonging to the same column, are electrically connected to a source line 5 of aluminum, for example, which extends over and along associated one of the well isolating regions 2. In the same way, the second active regions 7D, belonging to the same column, are electrically. connected to a bit line 4 of aluminum, for example, which also extends over and along associated one of the well isolating regions 2.
As shown in FIG. 24, the channel region 8 is located between each pair of (i.e., first and second) active regions 7S and 7D. Although not shown, a gate electrode is formed over the channel region 8 with a gate ferroelectric insulating thin film (which will be herein referred to simply as a xe2x80x9cferroelectric gate insulating filmxe2x80x9d) interposed therebetween. A word line 3, which extends over the well and well isolating regions 1 and 2 vertically to these regions 1 and 2, is electrically connected to the gate electrodes on the same row. It should be noted that a ferroelectric thin film, which has been formed in the same process step as the gate insulating film for MFSFETs (metal ferroelectric semiconductor FETs) 6, is interposed between these well and well isolating regions 1, 2 and the word line 3.
In this manner, MFSFETs 6, each being made up of the first and second active regions 7S and 7D, channel region 8, gate insulating film and gate electrode, are formed at intersections between each word line 3 and the respective well regions 1. As used herein, the MFSFET 6 is a field effect transistor including a ferroelectric gate insulating film.
Also, a well contact region 10 is provided on the surface of one end (e.g., the lower end) of each well region 1 and is electrically connected to an associated source line 5.
In the known ferroelectric memory, when data is written on an MFSFET 6 (i.e., one of the memory cells making up one of the number m of array blocks on the same column), a voltage is applied to the source line 5 provided in common for the number m of array blocks on the same column. In this case, the voltage, applied through the source line 5 to the well region 1, should travel all the way from the well contact region 10 to the MFSFET 6, on which data should be written, over a distance corresponding to an associated number of array blocks. Accordingly, an electric field, which has an intensity at least equivalent to the coercive force of the ferroelectric gate insulating film, is applied between the well region 1 and the gate electrode of the MFSFET 6 on which the data should be written. As a result, the ferroelectric thin film for the MFSFET 6 in question is reversed in polarization direction and the data can be written on the MFSFET 6 as intended.
In the known ferroelectric memory, the element isolating regions 9 are formed on the surface of each well region 1 at regular intervals. In addition, the first and second active regions 7S and 7D, which will be source and drain regions, respectively, are also defined between adjacent ones of the isolating regions 9 on the surface of each well region 1. Accordingly, the array of memory cells cannot have its total area reduced sufficiently.
Furthermore, the voltage, applied to the source line 5, should travel along a long path indicated by the broken line in FIG. 26. That is to say, the voltage must go all the way from the well contact region 10, which is far way from the MFSFET 6 where data should be written, to the well region 1 for the MFSFET 6. In addition, the resistance of the region to which the voltage is applied (i.e., the resistance of the well region 1) is higher than that of the aluminum lines or those of the active regions.
For that reason, it takes a long time for the voltage applied to the well contact region 10 to reach the well region 1 for the MFSFET 6 on which data should be written. That is to say, the write time is too long.
A first object of the present invention is reducing the total area of an array of memory cells.
A second object of the present invention is shortening the time needed to write data on an arbitrary MFSFET.
To achieve the first object, a first inventive ferroelectric memory includes: a well region, which is defined in a semiconductor substrate and extends in a direction; a bit line also extending in the direction; a source line also extending in the direction; first, second and third memory cells, which are formed in this order on the well region and arranged in the direction; a first active region for electrically connecting the first memory cell and the bit line together; a second active region for electrically connecting the first memory cell and the source line together; a third active region for electrically connecting the second memory cell and the bit line together; a fourth active region for electrically connecting the second memory cell and the source line together; a fifth active region for electrically connecting the third memory cell and the bit line together; and a sixth active region for electrically connecting the third memory cell and the source line together. In the memory, the first and third active regions are the same active region, and the fourth and sixth active regions are the same active region.
In the first inventive ferroelectric memory, the first active region for electrically connecting the first memory cell and the bit line together can be the same as the third active region for electrically connecting the second memory cell and the bit line together. In addition, the fourth active region for electrically connecting the second memory cell and the source line together can be the same as the sixth active region for electrically connecting the third memory cell and the source line together. That is to say, no isolating region is needed between the first and third active regions or between the fourth and sixth active regions. Accordingly, the length of a memory array as measured along the bit line can be reduced, and the overall area of the array can also be reduced considerably.
To achieve the second object, a second inventive ferroelectric memory includes: a well region, which is defined in a semiconductor substrate and extends in a direction; a source line also extending in the direction; and a plurality of well contact regions, which are formed discretely on the surface of the well region and electrically connect the well region and the source line together.
In the second inventive ferroelectric memory, multiple well contact regions are formed discretely on the surface of a single well region. Thus, compared to the known arrangement where a well contact region is formed outside of a memory array, it takes a much shorter time for a voltage applied to the source line to reach the well region of a target memory cell on which data should be written. Accordingly, the data can be written on the desired memory cell in a much shorter time.
To achieve the first and second objects, a third inventive ferroelectric memory includes: a well region of a first conductivity type, which is defined in a semiconductor substrate and extends in a direction; a source line also extending in the direction; an active region of a second conductivity type, which is formed as a source region on the surface of the well region; and a well contact region of the first conductivity type, which is formed on the surface of the well region. In the third memory, the active region and the well contact region are located adjacent to each other and connected to the source line via a single contact.
In the third inventive ferroelectric memory, an active region of a second conductivity type, which will be a source region, and a well contact region of a first conductivity type are located adjacent to each other. That is to say, no isolating region is provided between the active and well contact regions. Accordingly, the length of a memory array as measured along the bit line can be reduced, and the total area of the array can also be reduced considerably.
In addition, the active and well contact regions are not only located adjacent to each other but also connected to the source line via a single contact. Thus, compared to the known arrangement where a well contact region is formed outside of a memory array, it takes a much shorter time for a voltage applied to the source line to reach the well region of a target memory cell on which data should be written. Accordingly, the data can be written on the desired memory cell in a much shorter time.